This invention generally relates to iterative arithmetic processors, and more particularly to an apparatus capable of repeatedly performing the arithmetic operation of normalized floating-point numbers, at high speed and with less hardware.
Japanese Patent Application, which has been published under Pub. No. 1-195574 and whose corresponding U.S. application was granted a patent under U.S. Pat. No. 4,985,861, shows an iterative multiplication processor. This processor comprises a first converter for performing the conversion of a binary number into a singed digit (SD) number; an SD multiplier for performing the multiplication operation of two SD numbers to find a product represented in SD number representation; a register for holding a product represented in SD number representation; and a second converter for performing the conversion of an SD number into a binary number. The SD multiplier has two input ports, at one of which an SD number from the first converter is supplied and at the other of which an SD number from the register is supplied. This prior art multiplication processor realizes high-speed iterative multiplication operations by feeding a product represented in SD number representation back to the SD multiplier, without subjecting such a product to an SD-to-binary conversion process.
This prior art shows another iterative multiplication processor that further includes a single shifter. Such a shifter, however, is arranged outside the feedback loop and is provided between the register and the second converter.
IEEE Std 754 defines the notation system for the single precision binary floating-point number made up of 32 bits of which one bit indicates the sign S, eight bits indicate the exponent E, and the remaining 23 bits indicate the fraction F. The exponent E and the fraction F are adjusted in order that a virtual non-zero value bit (i.e., implied 1) and a binary point are positioned upward of the leftmost bit of the fraction F. This adjustment is called the normalization. A bias of 127 is added to an actual exponent to make such a biased exponent positive. In other words, a real number RN representing a single precision binary floating-point number can be written: EQU RN=(-1).sup.S 2.sup.E-127 (1.F) (1)
where 1.F represents a mantissa M. The mantissa M is a binary number made up of 24 digits including a non-zero value digit that is positioned upward one place from the binary point thereof, the magnitude of which is 1.ltoreq.M&lt;2.
Suppose that the latter iterative multiplication processor of the above-described prior art performs iterative multiplication operations in which the mantissa M of a normalized floating-point number serves as input data. In this case, it is only after the SD multiplier has completed every multiplication operation that the result of the arithmetic operation fetched from the register is right-shifted. A firstly-found product U.sub.1 by the SD multiplier falls within the range of 1.ltoreq.U.sub.1 &lt;2.sup.2, and when converted into a binary number, it may have a non-zero value digit that is positioned upward two places from the binary point thereof. This product U.sub.1 is stored in the register. A secondly-found product U.sub.2 falls within the range of 1.ltoreq.U.sub.2 &lt;2.sup.3, and, when converted into a binary number, it may have a non-zero value digit that is positioned upward three places from the binary point thereof. The register stores this product U.sub.2 in place of the previously found product U.sub.1. When input data supplied at one of the input ports of the SD multiplier and input data of the register are converted into binary numbers, the positions of their leftmost non-zero value digits are shifted to the left depending upon the multiplication repeat count. Therefore, the number of digits making up data to be processed by the SD multiplier and the register increases. As a result, when determining the size of circuitry for the SD multiplier and the register, the maximum value of the repeat count must previously be estimated. This produces the problem that the circuitry size increases with the repeat count.